Copper is favored as a conductive material used in interconnect features in advanced, high-speed semiconductor devices. Damascene and dual damascene interconnect technology is advantageously used to provide planarized interconnect structures in advanced semiconductor manufacturing technologies. In processing operations used to form damascene, dual damascene and other openings, a dielectric layer is etched to expose a protective layer or etch stop layer. The exposed layer may be disposed directly between a subjacent copper-containing conductive material and the environment. A shortcoming of the use of copper is that copper is susceptible to corrosion when exposed to the environment.
Dielectric etching operations use a photoresist film as an etch mask. After the conclusion of the etching operation used to form the damascene, dual damascene or other openings in the dielectric layer, a sequence of cleaning operations is used to remove the photoresist film and other undesired by-products and contaminants generated during the etching operation, and to clean and dry the semiconductor substrate. The phenomenon of copper corrosion could result during these cleaning operations or subsequent to the cleaning operations as a result of the condition of the substrate.
According to conventional processing methods, the post-etch cleaning operation typically includes a DI water cleaning step in which the semiconductor substrate is rotated at a relatively high spin speed, such as 500–1000 rpm. It has been found that the DI water cleaning step introduces a high potential gradient across the semiconductor substrate due to electrostatic charge build-up produced by friction between the semiconductor substrate surface and the DI water. This potential gradient induces breakdown of dielectric materials such as etch stop layers or other protective layers which separate a copper containing conductive material disposed beneath such layer, from the environment after the layer is exposed during the dielectric etching operation. The breakdown of such a layer exposes copper and leads to copper corrosion. The potential gradient also creates a battery circuit that, through galvanic effect, also causes copper corrosion. Copper corrosion causes device failure or at least device functionality problems.
It would therefore be desirable to provide a post-etch semiconductor substrate cleaning operation that effectively cleans the semiconductor substrate and does not cause copper corrosion.